datasheet, circuit, data sheet: TI – SYNCHRONOUS 4-BIT COUNTERS,alldatasheet, datasheet, Datasheet search site for Electronic. These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs. The DM74LSA and. 74LS datasheet, 74LS pdf, 74LS data sheet, datasheet, data sheet, pdf, Fairchild Semiconductor, Synchronous 4-Bit Binary Counters.
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Message 4 of Can you provide me with the following information to help the troubleshooting?
Question to the forum: Message 1 of For some reason i couldnt attach files with my message above, and i cannot post them separately either it appears They should form a simple 16 bit binary counter that keeps incrementing until all of the output bits for E4 are all zeros and then it loads all the counters with preset value.
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Message 7 of Message 5 of I am building a simulation of an old 70s design based on s and I have had a lot of trouble getting a set of counters to operate according to my expectations. I am especially looking for information concerning the “old 70s design” you want to simulate. When connected to ENT as it appears to be done in the orignal schematics p21, B4 to E4 the third counter starts to race at clock speed when RCO set ENT high as can be seen in the attached simulation screen shot.
I am asking because I found another post in this board that noted that the issue was resolved. Thanks in advance for your feedback! Message 10 of I am new to NI tools and new to the forums.
Message 9 of But, when the second counter’s RCO carries over to the third counters ENT it stays high for a long period of time the duration of the QA and sets off the third counter to “race at clock speed” similar to the datadheet counter.
Most Active Software Boards: Thanks for sharing these files over here!
Multisim and Ultiboard
Is the model that is being used in there shareable? Message 8 of In my search for understanding more I discovered a recent document that had identified an error in the multisim model related to the counter executing on falling edge of clock, should be rising edge.
Message 3 dwtasheet I appreciate any insights. Unfortunately it did not solve my headache.
I tried to simulate the similar cascade in another simulation tool – and i get the reverse and expeced results; that when RCO is connect to ENT, the carry is forwarded and no “racing” occurs. Please find attached the multisim model.
In the schematics the rco is connected to ENT. Something wrong with the model? Message 2 of This is not the case when connecting to ENP. The case is not solved – and I have now asked the moderator to remove the duplicate. Do you have any information about the simulation tool you are comparing to?