DS1225Y DATASHEET PDF

SEMICONDUCTOR. DSY. 64K Nonvolatile SRAM. PIN ASSIGNMENT. FEATURES. 10 years minimum data retention in the absence of external power. CC. DSY Datasheet, DSY 64k Nonvolatile SRAM Datasheet, buy DSY DSY datasheet, DSY pdf, DSY data sheet, datasheet, data sheet, pdf, Dallas Semiconductor, 64K Nonvolatile SRAM.

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If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

The unique address specified by the 13 address inputs A0—A12 defines which of the bytes of data is to be accessed.

Dallas, DSY Non-volatile SRAM

The expected tDR is defined as starting at the date of manufacture. The OE control signal should be kept inactive high during write cycles to avoid bus contention.

If WE is low or the WE low transition occurs prior to or datwsheet with the CE low transition, the output buffers remain in a high impedance state during this period.

All voltages are referenced to ground. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. Storage Temperature Lead Temperature soldering, 10s Note: AA designates the year of manufacture.

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The later-occurring falling edge dw1225y CE or WE will determine the start of the write cycle. During power—up, when VCC rises above approximately 3. AA designates the year of manufacture. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption.

DSY Datasheet pdf – 64K Nonvolatile SRAM – Dallas Semiconductor

If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. In a power down condition the voltage on any pin may datsaheet exceed the voltage on VCC. WE is high for a read cycle. During power-up, when VCC rises above approximately 3.

If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high-impedance state during this period. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

The unique address specified by the 13 address inputs A0-A12 defines which of the bytes of data is to be accessed. BB designates the ds1225h of manufacture.

The write cycle is terminated by the earlier rising edge of CE or WE. Exposure to absolute maximum rating conditions for extended periods dataseet time may affect reliability.

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Ds1225y datasheet pdf

All AC and DC electrical characteristics are valid over the full operating temperature range. In a power down condition the voltage on any pin may not exceed the voltage on VCC. WE is high for a read cycle. Under datassheet circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. Data is maintained in the absence of VCC without any additional support circuitry.

Exposure to absolute maximum dataasheet conditions for extended periods of time may affect reliability. The expected tDR is defined as starting at the date of manufacture. If the CE high transition occurs prior to or simultaneously with the WE high transition, the dw1225y buffers remain in a high impedance state during this period. EDIP is wave or hand soldered only.

Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. Documents Flashcards Grammar checker. All AC and DC electrical characteristics are valid over the full operating temperature range. All address inputs must be kept valid throughout the write cycle.